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Microelectronics
DESCRIPTION
The CE2746 is a mixed signal CMOS monolithic audio digital to analog converter. It contains six 1-bit sigma delta DAC. The system consists of 128-time interpolation filters, 4th order modulators, switch capacitors and analog reconstruction filters. The one bit converter offers superior differential linearity, with no distortion due to component mis-match. high tolerance to clock jitter. The CE2746 support data conversion from 32K to 192KHz. The analog section operates at 5 volt while the digital section at 3.3 volt. This dual voltage system reduces not only the power consumption but also the noise caused by the digital circuit switching. The CE2746 is ideal for DVD player, AV receiver and set-top box application. The CE2746 support 24, 20, 18 and 16-bit input data. It also support multiple sampling frequency data. Each DAC has its own individual volume control.
CE2746
6-Channel Audio DAC, 24-bit, 192kHz
FEATURES
* Six Channel Audio DAC. - 104 dB SNR (A Weighted). - -94 dB THD + N Ratio (A Weighted). - 8K - 192 KHz. Sampling Rates. - Independent Digital Volume Control. - I2S, Left and Right Justified Digital Input Formats. - On -chip Reconstruction Filters. * 3.3 -volt Digital Interface. * 2-wire Serial Control Interface. * 3.3 Volt Digital. 5 Volt Analog Power Supply.
Applications
* Digital Surround Sound For Home Theatre * DVD * Car Audio.
XCK
PLL
CE2746
Mod.
D/A D/A D/A D/A D/A D/A
AR1 AL1 AR2 AL2 AR3 AL3
DIN1 DIN2 DIN3
80 80 77
INTERPOLATION
DIGITAL AUDIO INPUT
FILTER
Mod. Mod.
LRCK BCK
77 78
Format Detect'n
Control
Interface
15
15
SDA
SCL
RST
VCM
CEI Microelectronics Co. Ltd.
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March 24, 2004
CE2746
DAC Performance
Item
1 2 3 4 5 6 7 8
PERFORMANCE SPECIFICATIONS
Audio Output Level Audio Bandwidth 20Hz - 20 KHz SNR (A-weight) THD + NOISE (A-weight, 0 dB input) Dynamic Range Channel Separation Nonlinear Distortion Channel Gain Error
Spec.
1 Vrms +/- 0.1 dB >104 dB < -88 dB 98 dB < -90 dB < 0.25 dB < 0.1 dB
All Measurement were taken with only one channel active.
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CE2746
XCK REQUIREMENT
The CE2746 supports 384 and 256 times sampling clock for 32, 44.1, 48, 96 and 192K audio; 192 or 128 times for the 96 K audio.; and 96 and 64 times for the 192K audio.
XCK Requirement
Sampling Rate XCK Freq. CREG1[5:4]=[0 0] Normal XCK fs 32 K 44.1 48 K 96 K 192 K 384*fs 12.288 MHz 16.934 Mhz 18.432 MHz 18.432 MHz 18.432 Mhz 256*fs 8.192 MHz 11.29 Mhz. 12.288 Mhz. 12.288 Mhz. 12.288 Mhz. CREG1[5:4]=[1 0] 4 times XCK 4*384*fs 49.152 MHz 67.738 Mhz 73.728 MHz 73.728 MHz 73.728 Mhz 4*256*fs 32.768 MHz 45.158 Mhz. 49.152 Mhz. 49.152 Mhz. 49.152 Mhz. CREG1[5:4]=[0 1] 2 times XCK 2*384*fs 24.576 MHz 33.869 Mhz 36.864 MHz 36.864 MHz 36.864 Mhz 2*256*fs 16.384 MHz 22.579 Mhz. 24.576 Mhz. 24.576 Mhz. 24.576 Mhz.
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CE2746
PIN ASSIGNMENT
DVDD XCK BCK LRCK DIN1 DIN2 DIN3 TST RSTZ N/C DGND TSTOUT SDA SCL 1 2 3 4 5 28 27 26 25 24 AVDD AR1 GR1 AL1 AGND AR2 GR2 AL2 AGND AR3 GR3 AL3 VCM AVDD
CE2746
6 7 8 9 10 11 12 13 14
23 22 21 20 19 18 17 16 15
PIN DESCRIPTION
Pin Name DIGITAL DVDD XCK BCK LRCk 1 2 3 4 +3.3V I I I Digital power supply, 3.3 Volt. External Master Clock Input. Audio Serial Data Clock Input. Left/Right Channel Clock pin. For Left justified or Right justified mode, a high in SF indicates Left Channel Data, a low in SF indicates Right Channel Data. For I2S mode, a low in SF indicates Left Channel Data, a high in SF indicates Right Channel Data. Channel 1 Serial Audio Data Input. Channel 2 Serial Audio Data Input. Channel 3 Serial Audio Data Input. Test pin. This pin should be connected to ground. Active Low Reset Pin. Open drain output with a 5 Kohms pull-up resistor. Should leave open if not connected to system reset. Not used. can connected to ground. Pin # Type Description
DIN1 DIN2 DIN3 TST RSTZ N/C
5 6 7 8 9 10
I I I I I/O
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CE2746
PIN DESCRIPTION (Continued)
Pin Name DGND TSTOUT SDA Pin # 11 12 13 Type GND T I/O Digital ground Tri-state output pin, This pin can be connected to ground or leave open I2C data bus. Open drain output. Externally this pin should tie to a 680 ohm pull up resistor. I2C clock input. Description
SCL Analog AVDD AR1 GR0 AL1 AGND AR2 GR1 AL2 AGND AR3 GR2 AL3 VCM AVDD
14
I
28 27 26 25 24 23 22 21 20 19 18 17 16 15
+5V O GND O GND O GND O GND O GND O I/O +5V
Analog circuits power supply.Should be Connected to a 22 uF capacitor in parallel with a 0.1 uF. Analog right channel 1 output Analog circuits ground Analog left channel 1 output Analog circuits ground Analog right channel 2 output Analog circuits ground Analog left channel 2 output Analog circuits ground Analog right channel 3 output Analog circuits ground Analog right channel 3 output Common voltage De-coupling Pin Should be Connected to a 22 uF capacitor in parallel with a 0.1 uF. Analog circuits power supply.Should be Connected to a 22 uF capacitor in parallel with a 0.1 uF.
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March 24, 2004
CE2746
DIGITAL AUDIO SERIAL INTERFACE
The digital serial interface consists of 3 serial input pins, DIN1, DIN2, DIN3, and one serial clock input pin, BCK, and one left/right indicator input pin, LRCK. The data are 2's complement MSB first numbers. The CE2746 supports four resolution, which are selected programming the control register CREG0[5:4] via the I2C serial control port. Table 1 describes these four resolution.
Table (1): Audio Serial Data Input Resolution,
Format 0 1 2 3 CREG0[5:4] 00 01 10 11 DIN[3:1] 24-bit (default) 20-bit 18-bit 16-bit
The DIN3, DIN2 and DIN1 can be either 24-bit or 32-bit per frame as well as left justified, right justified or I2S. The CE2746 counts the number of BCK per frame to determine whether the input is 24 or 32 bits format.
Table (2): Audio Serial Data Input Modes
Mode 0 1 2 3 CREG0[7:6] 00 01 10 11 DIN[3:1] Right Justified I2S Left Justified (default) Invalid
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CE2746
Figure 1. Audio Serial Input Data Timing Diagram
1/fs
LRCK BCK MSB DIN1,2,3
LEFT CHANNEL
RIGHT CHANNEL
LSB
2 1 0
MSB
2 1
LSB
0
Right justified, CREG0[7,6]=[0 0] LEFT CHANNEL 1/fs RIGHT CHANNEL
LRCK BCK MSB DIN1,2,3
LSB
0
MSB
1
LSB
0
Left justified, CREG0[7,6]=[1 0] LEFT CHANNEL 1/fs RIGHT CHANNEL
LRCK BCK MSB DIN1,2,3
LSB
1 0
MSB
1
LSB
0
I2S, CREG0[7,6]=[0 1]
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CE2746
INFINITE ZERO DETECTION
The CE2746 has an Infinite Zero Detection circuit which detects zero in the Audio Serial Port that lasts for approximately 0.2 sec. By default, the zero detection circuit is on.
Serial Command Port
The user can select the chip operation mode by programming the internal control registers through serial I2C port. The Chip Address for the CE2746 is 35H. The protocol for write operation consists of sending 3 byte data to CE2746, following each byte is the acknowledges generated by CE2746. The first byte is the 7-bit Chip Address followed by the read/write bit (read is high, write is low). The second byte is the control register address. The third byte is the control register data. Upon power up, all programmable registers are set to default values. Figure 2 describes the serial command port timing relationship.
Figure 2. Serial Command Port Timing
I 2 C Bus Control Register Write Example:
first byte
Start CA6 CA0 R/W ACK A7
second byte
A0 ACK D7
third byte
D0 ACK Stop
SDA
1 1 1 1
SCL
Example Set channel 1L volume to 30H: first byte: [CA R/W] = 6AH
( Note: Chip adrress: CA<6:0> = 35H, R/W =0.)
second byte: register address: A<7:0> = 02H third byte: data D<7:0> = 30H
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CE2746
SERIAL PORT CONTROL REGISTER ASSIGNMENT
There are 8 registers dedicated to the CE2746 for chip functional programming, The register addresses assignments are
Address (decimal) 0 1 2 3 4 5 6 7
Register CREG0[7:0] CREG1[7:0] VOLREG0[7:0] VOLREG1[7:0] VOLREG2[7:0] VOLREG3[7:0] VOLREG4[7:0] VOLREG5[7:0]
Default Value 81 80 80 80 80 80 80 80
Register Function Data input format, de-emphasis filter selection Input format and PLL output frequency selection Volume control for channel 1, left Volume control for channel 1, right Volume control for channel 2, left Volume control for channel 2, right Volume control for channel 3, left Volume control for channel 3, right
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CE2746
CONTROL REGISTERS DESCRIPTION Control Register 0(ADRS=hex00, default=hex81)
CREG0[7:0] ADDR[3:0] BIT 7 Hex 00 Default Value R/W 1 R/W LF BIT 6 I2S 0 R/W 0 R/W BIT 5 BIT 4 BIT 3 AMUTE 0 R/W 0 R/W BIT 2 DEEMP 0 R/W 0 R/W BIT 1 BIT 0
FMT[1:0]
FSMPL[1:0] 1 R/W
[LF, I2S] Digital Serial Bus Format Select 00: - Normal or Right Justified Format. 01: - I2S Format. 10: - Left Justified Format. (default) 11: - Not allowed. FMT[1:0]: - These two bits define the serial audio input resolution 00: - 24-bit resolution. (default) 01: - 20-bit resolution. 10: - 18-bit resolution. 11: - 16-bit resolution. AMUTE: - Auto-mute detection enable. 0: - Auto-mute enabled. (default) 1: - No auto-mute. DEEMP: - Enable de-emphasis (active only when FSMPL is 2'b00). 0: - Normal. (default) 1: - enable de-emphasis when FSMPL is 0. FSMPL: - Sampling rate: 00: - 44.1 K sampling. 01: - 48K sampling. (default) 10: - 96K sampling. 11: - 192K sampling.
Control Register 1 (ADRS=hex01, default=hex80)
CREG1[7:0] ADDR[3:0] BIT 7 Hex 01 Default Value R/W
AUTODET
BIT 6 FS384 0 R/W
BIT 5 CKDIV4 0 R/W
BIT 4 CKDIV2 0 R/W
BIT 3
BIT 2 MUTE56 0 R/W
BIT 1 MUTE34 0 R/W
BIT 0 MUTE12 0 R/W
spare
0 R/W
1 R/W
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CE2746
AUTODET Automatically detects the serial audio input data sampling rate 0: - do not use auto-detect 1: - automatically detects the serial audio input data sampling rate. FS384: 384 fs or 256 fs control for the PLL clock output 0: the PLL takes the reference clock and multiplies it by 2 to generate a 512 bit clock 1: the PLL takes the reference clock and multiplies it by 4/3 to generate a 512 bit clock CKDIV4: Clock divider enable control 0: do not enable input clock divided by 4 1: enable input clock divided by 4 CKDIV2: Clock divider enable control 0: do not enable input clock divided by 2 1: enable input clock divided by 2 MUTE56: Mute control for channels 5 and 6 0: do not mute channels 5 and 6 1: simultaneously mute channels 5 and 6 MUTE34: Mute control for channels 3 and 4 0: do not mute channels 3 and 4 1: simultaneously mute channels 3 and 4 MUTE12: Mute control for channels 1 and 2 0: do not mute channels 1 and 2 1: simultaneously mute channels1 and2
Volume Registers for channel 1 to channel 3, (ADRS=hex02 - hex07, default=hex80)
Volume Registers ADDR[3:0] BIT 7 Hex 02 Hex 03 Hex 04 Hex 05 Hex 06 Hex 07 Default Value BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Channel 1 left volume register, VOLREGL1[7:0] Channel 1 right volume register, VOLREGR1[7:0] Channel 2 left volume register, VOLREGL2[7:0] Channel 2 right volume register, VOLREGR2[7:0] Channel 3 left volume register, VOLREGL3[7:0] Channel 3 right volume register, VOLREGR3[7:0] 1 0 0 0 0 0 0 0
VOLREG:- Control the volume of the 6 DAC's 80h- corresponds to 0 dB setting. Value should not be programed greater than 80h.
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CE2746
APPLICATION CONNECTION EXAMPLE:
Digital 3.3 Volt 22 uF 2 Over Sample Clock 3 4 Digital Audio Interface 5 6 7 +3.3 Volt 680 ohm I 2 C Serial Interface 13 14 8 9 RST DGND All Unmarked Capacitors have values of 0.1 uF 11 AGND 20 24 SDA SCL TST GR1 26 GR2 22 GR3 18 VCM XCK BCK LRCK AL1 DIN1 DIN2 DIN3 AR2 AL2 AR3 1 DVDD 15 AVDD AVDD 28 AR1 27 25 23 21 19 17 16
22 uF
Analog +5 Volt
22 uF
CE2746
AL3
22 uF
Reset
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CE2746
SUGGESTED ANALOG RECONSTRUCTION FILTER
A second Sallen Key low pass reconstruction filter is recommend to remove the high frequency sigma delta modulator noise. The filter's component values and characteristic are shown in the following figures.
Sallen Key 2nd order LP filter
1000 pF
4.7 uF
2.7 K
10 K + 680 pF 10 K 10 K
100 K
All resistors and capicitors are 5% precision.
LP F F requenc y Res pons e 5 0 -5 Amplitude (dB) -10 -15 -20 -25 -30 10
3
10
4
10 F req (H z .)
5
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March 24, 2004
TIMING DIAGRAM
SDA
SCL
t D
CE2746
Figure 3. Audio Serial Interface Timing Requirement
tbck tbck
Htkd L
su
hdtkr
su
hd
Figure 4. Serial Command Port Write Timing Requirement
tSCL
tLOW
tHIGH
SDA, SCL
tF
tR
tBF
tHD,sta
tHD,dat
tSU,dat
tSU,sta
tSU,stp
stop
start
start
stop
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CE2746
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Vi Ai Vo Ao TDsc TASC Ta Tj Tsol Tvsol Tstor Notes:
Characteristics Power Supply Voltage (Measured to GND) Digital Input Applied Voltage2 Digital Input Forced Current3,4 Digital Output Applied Voltage2 Digital Output Forced Current3,4
Digital Short Circuit Duration (single output high state to Vss)
Min -0.5 GND-0.5 -100 GND-0.5 -100
Max +7.0
Units V V
100 VDD+0.5 100 1 infinite
mA V mA Sec Sec
o o o o o
Analog Short Circuit Duration (single output to VSS1) Ambient Operating Temperature Range Junction Temperature (Plastic Package) Lead Soldering Temperature (10 sec., 1/4" from pin) Vapor Phase Soldering (1 minute) Storage Temperature -65 -25 -65
+125 +150 280 220 +150
C C C C C
1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
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CE2746
ELECTRICAL CHARACTERISTICS
Parameter Power Supply AVDD DVDD IDA IDD
Characteristics
Min
Typ
Max
Units
Analog power supply voltage Digital power supply voltage Analog Current Digital Current
4.5 3.0
5 3.3 60 20
5.5 3.6
V V mA mA
Audio DAC Characteristics Full Scale Output Voltage to a 10K load VVCM Reference voltage .98 1 2.25 1.02 2.41 Vrms V
Digital Characteristics VIH IOZH IOZL CI CO Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. Hi-Z Leakage Current, HIGH, VDD=Max, VIN=3.3 Volt Hi-Z Leakage Current, LOW, VDD=Max, VIN=VSS) Digital Input Capacitance (TA=25oC, f=1Mhz) Digital Output Capacitance (TA=25oC, f=1Mhz) 2.0 VDD 33 -10 8 10 V
A A
pF pF
Audio Serial Interface Timing
tbck
BCK Cycle Time BCK Pulse Width, HIGH BCK Pulse Width, LOW Audio Data Setup Time With Respect To Rising Edge of BCK Audio Data Hold Time With Respect to Rising Edge of BCK Audio LRCK Setup Time With Respect To Rising Edge of BCK
80 30 30 10 15 10
ns ns ns ns ns ns
tbckH tbckL tkdsu tkdhd tkrsu
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CE2746
Parameter tkrhd
Characteristics Audio LRCK Hold Time With Respect To Rising Edge of BCK
Min 15
Typ
Max
Units ns
Serial Command Port
fSCL tSU,sta tHD,sta tSU,stp tLOW tHIGH tR tF tSU,DAT tHD,DAT tBF
SCL Clock Frequency Start condition set up time Start condition hold time Stop condition set up time SCL Low time SCL High time SCL & SDA rise time SCL & SDA fall time Data set-up time Data hold time Bus Free time 250 0 4.7 4.7 4.0 4.0 4.7 4.0
100
kHz us us us us us
1.0 0.3
us us ns ns us
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CE2746
PACKAGING INFORMATION Dimensions
mm. min A A1 norm max min mm. norm max
2.13 0.05 0.22 0.09 9.90 10.20 0.3 0.25 0.38 0.20 10.50
E1 E2
5.0 7.4
5.3 7.8 0.65
5.6 8.2
b C
D
e
L
0.63
0.9
1.03
28-Pin (SSOP)
D
E1
E2
A1
A
b
e c L
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March 24, 2004

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